1 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o may 2004 2003 integrated device technology, inc. dsc-5737/8 c idt74sstv16857 industrial temperature range functional block diagram 14-bit registered buffer with sstl i/o description: the sstv16857 is a 14-bit registered buffer designed for 2.3v-2.7v v dd for pc1600-pc2700, and 2.5v-2.7v v dd for pc3200, and supports low standby operation. all data inputs and outputs are sstl_2 level compatible with jedec standard for sstl_2. reset is an lvcmos input since it must operate predictably during the power-up phase. reset , which can be operated independent of clk and clk , must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. reset , when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. with inputs held low and a stable clock applied, outputs will remain low during the low-to-high transition of reset . features: ? 1:1 registered buffer ? meets or exceeds jedec standards for sstv16857 and sstvn16857 ? 2.3v to 2.7v operation for pc1600, pc2100, and pc2700 ? 2.5v to 2.7v operation for pc3200 ? sstl_2 class ii style data inputs/outputs ? differential clk input ? reset control compatible with lvcmos levels ? flow-through architecture for optimum pcb design ? drive up to equivalent of 18 sdram loads ? latch-up performance exceeds 100ma ? esd >2000v per mil-std-883, method 3015; >200v using machine model (c = 200pf, r = 0) ? available in tssop package the idt logo is a registered trademark of integrated device technology, inc. applications: ? along with cspt857c/d, zero delay pll clock buffer, provides complete solution for ddr1 dimms 34 38 39 35 48 r 1d c1 1 q1 reset ck ck v ref d1 to 13 other channels
2 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o pin configuration tssop top view absolute maximum ratings (1) symbol description max. unit v dd or v ddq supply voltage range ?0.5 to 3.6 v v i (2) input voltage range ?0.5 to v dd +0.5 v v o (3) output voltage range ?0.5 to v ddq +0.5 v i ik input clamp current, v i < 0 ?50 ma i ok output clamp current, 50 ma v o < 0 or v o > v ddq i o continuous output current, 50 ma v o = 0 to v ddq v dd continuous current through each 100 ma v dd , v ddq or gnd t stg storage temperature range ?65 to +150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. 3. the output current will flow if the following conditions are observed: a) output in high state b) v o = v ddq function table (1) input reset clk clk d q outputs h ll h hh h l or h l or h x q (2) lx x x l notes: 1. h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2. q = output level before the indicated steady-state conditions were established. 48 1 q 1 d 1 247 q 2 d 2 gnd 346gnd v ddq 445 v dd 5 44 q 3 d 3 643 q 4 d 4 742 q 5 d 5 gnd 841d 6 v ddq 9 40 d 7 10 39 q 6 clk 11 38 q 7 clk 12 37 v dd v ddq gnd 13 36 gnd 14 35 q 8 v ref 15 34 q 9 reset 16 33 v ddq d 8 17 32 gnd d 9 18 31 q 10 d 10 19 30 q 11 d 11 20 29 q 12 d 12 21 28 v dd v ddq 22 27 gnd gnd 23 26 q 13 d 13 24 25 q 14 d 14
3 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o symbol parameter test conditions min. typ. max. unit v ik control inputs v dd = 2.3v, i i = ? 18ma ? ? ?1.2 v v oh v dd = 2.3v to 2.7v, i oh = -100 av dd ? 0.2 ? ? v v dd = 2.3v, i oh = -16ma 1.95 ? ? v ol v dd = 2.3v to 2.7v, i ol = 100 a ? ? 0.2 v v dd = 2.3v, i ol = 16ma ? ? 0.35 i i all inputs v dd = 2.7v, vi = v dd or gnd ? ? 5 a i dd static standby i o = 0, v dd = 2.7v, reset = gnd ? ? 0.01 ma static operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ??? i ddd dynamic operating (clock only) i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,??? a/clock clk and clk switching 50% duty cycle. mhz dynamic operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,??? a/clock (per each data input) clk and clk switching 50% duty cycle. one data input mhz/data switching at half clock frequency, 50% duty cycle. input r oh output high v dd = 2.3v to 2.7v, i oh = -20ma 7 ? 20 r ol output low v dd = 2.3v to 2.7v, i oh = 20ma 7 ? 20 r o( ) | r oh - r ol | each separate bit v dd = 2.5v, t a = 25c, i oh = -20ma ? ? 4 data inputs v dd = 2.5v, v i = v ref 310mv 2.5 ? 3.5 c i clk and clk v icr = 1.25v, v i (pp) = 360mv 2.5 ? 3.5 pf reset v i = v dd or gnd ? ? ? dc electrical characteristics over operating range (pc1600-pc2700) following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c, v dd = 2.5v 0.2v, v ddq = 2.5v 0.2v symbol parameter test conditions min. typ. max. unit v ik control inputs v dd = 2.5v, i i = ? 18ma ? ? ?1.2 v v oh v dd = 2.5v to 2.7v, i oh = -100 av dd ? 0.2 ? ? v v dd = 2.5v, i oh = -16ma 1.95 ? ? v ol v dd = 2.5v to 2.7v, i ol = 100 a ? ? 0.2 v v dd = 2.5v, i ol = 16ma ? ? 0.35 i i all inputs v dd = 2.7v, vi = v dd or gnd ? ? 5 a i dd static standby i o = 0, v dd = 2.7v, reset = gnd ? ? 0.01 ma static operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ??? i ddd dynamic operating (clock only) i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,??? a/clock clk and clk switching 50% duty cycle. mhz dynamic operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,??? a/clock (per each data input) clk and clk switching 50% duty cycle. one data input mhz/data switching at half clock frequency, 50% duty cycle. input r oh output high v dd = 2.5v to 2.7v, i oh = -20ma 7 ? 20 r ol output low v dd = 2.5v to 2.7v, i oh = 20ma 7 ? 20 r o( ) | r oh - r ol | each separate bit v dd = 2.6v, t a = 25c, i oh = -20ma ? ? 4 data inputs v dd = 2.6v, v i = v ref 310mv 2.5 ? 3.5 c i clk and clk v icr = 1.3v, v i (pp) = 360mv 2.5 ? 3.5 pf reset v i = v dd or gnd ? ? ? dc electrical characteristics over operating range (pc3200) following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c, v dd = 2.6v 0.1v, v ddq = 2.6v 0.1v
4 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o operating characteristics (pc1600-pc2700), t a = 25oc (1) symbol parameter min. typ. max. unit v dd supply voltage v ddq ? 2.7 v v ddq output supply voltage 2.3 2.5 2.7 v v ref reference voltage (v ref = v ddq /2) 1.15 1.25 1.35 v v tt termination voltage v ref ? 40mv v ref v ref + 40mv v v i input voltage 0 ? v dd v v ih ac high-level input voltage data inputs v ref + 310mv ? ? v v il ac low-level input voltage data inputs ? ? v ref ? 310mv v v ih dc high-level input voltage data inputs v ref + 150mv ? ? v v il dc low-level input voltage data inputs ? ? v ref ? 150mv v v ih high-level input voltage reset 1.7 ? ? v v il low-level input voltage reset ? ? 0.7 v v icr common-mode input range clk, clk 0.97 ? 1.53 v v i (pp) peak-to-peak input voltage clk, clk 360 ? ? mv i oh high-level output current ? ? ? 20 ma i ol low-level output current ? ? 20 t a operating free-air temperature ? 40 ? +85 c note: 1. the reset input of the device must be held at v dd or gnd to ensure proper device operation. operating characteristics (pc3200), t a = 25oc (1) symbol parameter min. typ. max. unit v dd supply voltage v ddq ? 2.7 v v ddq output supply voltage 2.5 2.5 2.7 v v ref reference voltage (v ref = v ddq /2) 1.25 1.3 1.35 v v tt termination voltage v ref ? 40mv v ref v ref + 40mv v v i input voltage 0 ? v dd v v ih ac high-level input voltage data inputs v ref + 310mv ? ? v v il ac low-level input voltage data inputs ? ? v ref ? 310mv v v ih dc high-level input voltage data inputs v ref + 150mv ? ? v v il dc low-level input voltage data inputs ? ? v ref ? 150mv v v ih high-level input voltage reset 1.7 ? ? v v il low-level input voltage reset ? ? 0.7 v v icr common-mode input range clk, clk 0.97 ? 1.53 v v i (pp) peak-to-peak input voltage clk, clk 360 ? ? mv i oh high-level output current ? ? ? 20 ma i ol low-level output current ? ? 20 t a operating free-air temperature ? 40 ? +85 c note: 1. the reset input of the device must be held at v dd or gnd to ensure proper device operation.
5 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o timing requirements over recommended operating free-air temperature range pc1600 - pc2700 pc3200 symbol parameter min. max. min. max. unit clock clock frequency ? 200 ? 220 mhz tw pulse duration, clk, clk high or low 2.5 ? 2.5 ? ns t act differential inputs active time (1) ?22?22ns t inact differential inputs inactive time (2) ?22?22ns t su setup time, fast slew rate (3, 5) data before clk , clk 0.65 ? 0.65 ? ns setup time, slow slew rate (4, 5) 0.75 ? 0.75 ? ns t h hold time, fast slew rate (3,5) data before clk , clk 0.75 ? 0.75 ? ns hold time, slow slew rate (2,5) 0.9 ? 0.9 ? ns switching characteristics over recommended free-air operating range (unless otherwise noted) pc1600 - pc2700 pc3200 symbol parameter min. max. min. max. unit f max 200 ? 220 ? m h z t pdm clk and clk to q 1.1 2.8 1.1 2.4 (1) ns t pdmss clk and clk to q (simultaneous switching) ? ? ? 2.7 ns t phl reset to q ? 5 ? 5 ns notes: 1. data inputs must be low a minimum time of t act max., after reset is taken high. 2. data and clock inputs must be held at valid levels (not floating) a minimum time of t inact max., after reset is taken low. 3. for data signal input slew rate is 1v/ns. 4. for data signal input slew rate is 0.5v/ns and <1v/ns. 5. clk, clk signal input slew rates are 1v/ns. note: 1. 2.8ns for parts assembled and tested prior to ww14, 2004.
6 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o test circuits and waveforms for pc1600-pc2700, v dd = 2.5v 0.2v for pc3200, v dd = 2.6v 0.1v voltage waveforms - pulse duration notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0ma. 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v ddq /2 6. v ih = v ref + 310mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 310mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. t plh and t phl are the same as t pd . load circuit voltage waveforms - setup and hold times voltage waveforms - propagation delay times voltage waveforms - propagation delay times voltage and current waveforms inputs active and inactive times timing input v icr v i(pp) t plh t phl output v oh v ol v icr v tt v tt v oh v ol v ih v il t phl v dd /2 v tt lvcmos reset input output v ref v ih v il v ref input t w v ref v ih v il v ref input v icr v i(pp) t su t n timing input from output under test v tt r l =50 c l =30pf (see note 1) test point lvcmos reset input v dd /2 v dd t inact t act i dd v dd /2 90% 0v (see note 2) 10%
7 industrial temperature range idt74sstv16857 14-bit registered buffer with sstl i/o ordering information idt xx xxxx xx package device type temp. range pa pag thin shrink small outline package tssop - green 74 14-bit registered buffer with sstl i/o ?40c to +85c sstv 857 16 xx family double-density corporate headquarters for sales: san jose, ca 95138 fax: 408-284-2775 www.idt.com
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